This demo manifests different features of MC such as
operator merging, carrysave features, auto-pipelining
,etc, and how each of these contribute in improving
a design's delay and area goals. Also, the last module
of this demo, explores MC's ResolveLatency() and
ResolveLatencyLoop() which are highly useful while using
auto-pipelining.

This demo has 5 different modules.
Each module is in its own source file, ...
        MAC0.mcl, MAC1.mcl, MAC2.mcl, MAC3.mcl and MAC4.mcl.
Each of these describes a Multiply-Accumulate Circuit.
 
Each of the five modules can be demo'd in order.
In each case, click in the "Parameters" field.
Then type Ctrl-U to clear the line.
Pull down the "File" menu and select "Get Parameters".
This will extract the default parameters from the
module.  For demo purposes the default parameter
values can be used as is.
 
The demo will start with MAC0.mcl.  This is a simple
MAC design that does not use any operator merging, carrysave
or auto- pipelining features of MC. The results that one
gets from optimizing this design with MC will be almost
the same as DC results.
  
Next, change the file name to MAC1.mcl, clear the
parameters and change it to new ones if needed.
In MAC1.mcl, we exploit MC's operator merging capability
and check how it gives a better timing. However, this design 
is not suitable for pipelining the MAC's multilpier as well
as adder. 
 
Next, change the file name to MAC2.mcl.  
In this module we exploit MC's carrysave feature. Using
this we get better timing and also now the design can be
pipelined. (at least the multiplier can be pipelined).

Next, change the file name to MAC3.mcl.
Here, we use MC's carrysave "convert" feature which helps
us in pipelining the design better in this case and reduces
the critical path delay, thereby improving the overall timing.

Next, change the file name to MAC4.mcl.
Lastly, in MAC4.mcl, we have explored MC's auto-pipelining
feature to achieve better timing as well as used
ResolveLatency() and ResolveLatencyLoop() for setting
the number of pipe stages needed in different sections
of the design. The delay and latecny figures used here are for lca500k
technology library. You may have to change these figures to suit
the techbology that you are using.
 
Automatic pipelining can be used for any of the other designs too.  
From the "Synthesis" pull down menu, select "Pipeline".  
In the "Optimization" field enter the delay goal in ps.

